1. Field of the Invention
The invention relates to the field of semiconductor technology and, more particularly, to a CMOS-based lateral bipolar junction transistor (lateral BJT) with reduced base resistance.
2. Description of the Prior Art
Bipolar junction transistors or bipolar transistors, which are formed using a CMOS compatible process, are well known in the art. These bipolar transistors are also referred to as lateral bipolar junction transistors and have high threshold frequency (Ft) and high beta.
In the design of semiconductor integrated circuits, it is often desirable to provide a mixed mode device, i.e., which has both BJT and CMOS functions. Mixed mode devices both increase the flexibility of the IC design and increase the performance of the IC. The integration of CMOS transistors with bipolar transistors to provide Bipolar-CMOS (BiCMOS) integrated circuits is now well established. BiCMOS circuits provide advantages such as high speed, high drive, mixed voltage performance with analog-digital capabilities, which are beneficial in applications such as telecommunications. However, there is considerable challenge in optimizing the performance of both CMOS and bipolar devices fabricated with progressively reduced dimensions. In order to fabricate an integrated circuit combining both bipolar transistors and field effect transistors on the same chip, compromises must be made during both design and fabrication to optimize performance of both bipolar and field effect transistors, without inordinately increasing the number of processing steps.
The lateral bipolar transistor is fabricated using a typical lightly doped drain (LDD) MOS transistor. An NPN device is formed from an NMOS transistor and a PNP device is formed from a PMOS transistor. The base width of the lateral bipolar transistor is determined by and is usually equal to the MOS channel length. It is desirable to have a CMOS-based bipolar transistor having improved bipolar performance, such as reduced base resistance.